1. Field of the Invention
The present invention generally relates to testing of electrical circuits, particularly integrated circuits, and more specifically to a method and system for measuring the amount of electrical charge effectively arising at a circuit node (e.g., from a radiation strike) that is necessary to induce a change in the logical state of the circuit.
2. Description of the Related Art
Data processing systems such as general-purpose computers or special-purpose devices have many different storage elements including memory arrays for mass storage of program instructions and operand data, and registers which temporarily store values used by execution units during the functional operation of the device. A typical microprocessor contains many storage elements that represent the current state or operating mode of the machine at any given time. These storage elements are very critical for correct operation of the processor and any error in the data stored in these elements can easily lead to machine failure. Microprocessors also use latches to store ancillary information, including scan latches that are employed in level-sensitive scan design (LSSD) type systems. These systems generally allow information to be read from or written to the scan latches during operation of the data processing system in a separate clock domain.
Information stored in scan latches may include control, status or mode bits. For example, a data processing system might provide different mode configurations for clock control logic, and clock control latches can account for a significant portion of a microprocessor latch count. Microprocessors typically use control logic in local clock buffers to adjust the duty cycle and edge stressing of various clock pulses in the system and thereby meet the requirements of the local logic circuits. These clock buffer modes are set at system power-on using a scan controller, and often must maintain their logical value for days or months to ensure proper performance of the local logic circuits. However, these values can be upset during microprocessor operation due to a soft-error caused by stray cosmic radiation or alpha particles emitted from semiconductor packaging materials. The upset may be correctable by scanning in a new value, but systems may only allow scanning in a limited manner such as at power-on, meaning that the system must be restarted if a clock control latch becomes incorrectly set.
Soft errors have become a primary reliability concern in scaled technologies. These errors are often caused by alpha particle strikes emitted from packaging materials or by neutrons originating from cosmic radiation. The soft-error rate (SER) of a data processing system can exceed the combined failure rate of all hard-reliability mechanisms (gate oxide breakdown, electro-migration, etc.). Built-in soft-error protection has thus become a necessity for meeting robustness targets in advanced computer systems. All storage elements (random-access memory, latches, etc.) are highly susceptible to soft-error induced failures, but memory arrays are usually protected by error-correction codes (ECCs) while latches are usually not so protected. Soft errors in latches are accordingly the major contributors to overall system SER.
In one typical latch design data is stored in a cross-coupled inverter circuit. The state of this circuit is easily flipped by an alpha particle strike and in simple latches the data corruption occurs without detection. Once flipped, the state of the latch cannot be recovered. Combinational logic is typically more robust than sequential elements, i.e., static logic will eventually recover from an alpha strike, but a downstream error will arise if the temporary error induced in the logic arrives at a destination latch within the setup and hold time of that latch.
In order to devise better strategies for SER reduction, it is useful to understand the soft-error mechanism and in particular the smallest amount of charge that must be collected at a circuit node from a radiation strike in order to change the logical state of a latch. This critical charge, referred to as QCRIT, is a factor in determining the failure-in-time rate of the circuit. A higher QCRIT often means a more robust circuit. Researchers currently utilize expensive and time-consuming particle beam experiments to find the critical charges for particular circuits of interest. This method requires the fabrication of very large circuit macros (e.g., tens of thousands of instance of each circuit structure to be analyzed) in order to gather statistics by radiating the entire test structure with the particle beam, but many approximations and assumptions must be made in the extraction of QCRIT from such experiments. Furthermore, there are several difficulties with these experiments. They require a large and expensive particle accelerator, and must be planned and scheduled months in advance. Moreover, it is impossible to know the exact node of the circuit under test that was struck by a particle of the beam which leaves further guesswork in the analysis.
Another method for determining the robustness of a storage circuit in relation to induced soft errors is presented in U.S. Pat. No. 5,982,691. The QCRIT measurement is based on an equivalent diode structure which is impinged by a light pulse. This approach is also fraught with difficulties such as estimating the energies of alpha-particle strikes, computing absorption coefficients for silicon, and determining the amount of current that flows through the diode. It also requires specialized off-chip testing equipment.
A third method for evaluating the robustness of a logic circuit is disclosed in U.S. Pat. No. 6,330,182 involving the use of a current source which produces a current wave at a node in a logic circuit meant to model that induced by particle strikes. The integration over time of the current wave with the smallest amplitude resulting in a flip of the output logic level of the circuit under test would be equal to QCRIT, but the patent makes no mention of any physical implementation of this method for hardware testing purposes, nor does it account for the fact that producing a current pulse representative of those created by high-energy particle strikes is practically impossible with on-chip equipment.
In light of the foregoing, it would be desirable to devise an improved method for estimating the QCRIT of a logical circuit which does not require extensive off-chip instrumentation but still provides reliable results for further research into SER reduction and circuit design. It would be further advantageous if the method could more accurately pinpoint the particular node of the logical circuit which initiates an upset.